Generally, nonvolatile memory devices do not lose their stored data even though their power is turned off. These nonvolatile memory devices usually include flash memory cells that have a stacked gate structure. The stacked gate structure typically includes a tunnel oxide film, a floating gate, an inter-gate dielectric layer and a control gate electrode stacked sequentially. To improve reliability of the flash memory cell and efficiency of program, the quality of the tunnel oxide film may be improved and the coupling ratio of a cell may be increased.
Some nonvolatile memory devices may use phase changeable memory devices instead of the flash memory devices. FIG. 1 illustrates an equivalent circuit of a unit cell of a conventional phase changeable memory device. Referring now to FIG. 1, the phase changeable memory cell includes an access transistor TA and a variable resistor C. The variable resistor C includes a lower electrode, an upper electrode, and a phase changeable material layer interposed between the lower electrode and the upper electrode. The upper electrode of the variable resistor C is connected to a plate electrode PL. In addition, the access transistor TA includes a source region connected to the lower electrode, a drain region spaced apart from the source region, and a gate electrode on a channel region between the source region and the drain region. The gate electrode and the drain region of the access transistor TA are connected to a word line WL and a bit line BL, respectively. Consequently, the equivalent circuit of the phase changeable memory cell is similar to an equivalent circuit of a DRAM cell. The phase changeable material film is different from that of a dielectric film used in a DRAM, however. More specifically, the phase changeable material film has two stable states according to temperature.
FIG. 2 is a graph that illustrates a method of programming and erasing the phase changeable memory cell. Here, the horizontal axis corresponds to time T and the vertical axis corresponds to temperature TMP that is applied to the phase changeable material film. Referring now to FIG. 2, when the phase changeable material film is heated to a temperature higher than the melting temperature Tm during a first duration T1 and cooled, the phase changeable material film becomes amorphous (1). When the phase changeable material film is heated to a temperature higher than the crystallization temperature Tc but lower than the melting temperature Tm during a second duration T2 longer than the first duration and cooled, the phase changeable material film is crystallized (2). The specific resistance of the amorphous phase changeable material film is higher than that of the crystalline phase changeable material film. Accordingly, the current flowing through the phase changeable material film is detected during read mode so that it is determined whether the information stored in the phase changeable memory cell is logic “1” or “0.”A compound material layer that includes germanium (Ge), tellurium (Te), and stibium (Sb) (hereafter, referred to as GTS) is usually used as the phase changeable material film.
A method of reducing contact area between an electrode and a phase changeable material to improve the efficiency of the phase changeable memory device is disclosed in U.S. Pat. No. 6,117,720 entitled “Method of Making an Integrated Circuit Electrode Having a Reduced Contact Area.”
FIG. 3 is a cross-sectional view of a conventional phase changeable memory device 30. The conventional phase changeable memory device 30 includes a lower electrode 10 formed on a semiconductor substrate and an interlayer insulating film 12 having openings on the lower electrode 10. The opening is provided with a plug 14 connected electrically to the lower electrode 10 therein. The opening on the plug 14 is provided with a spacer 16 on the sidewall of the opening. A contact portion 18 connected to the plug 14 is positioned on the area surrounded by the spacer 16. The contact portion 18 can be formed using a phase changeable material and/or a conductive material. If the contact portion 18 is formed using a phase changeable material, then an upper electrode 20 is disposed on the interlayer insulating film 12 and the contact portion 18. If the contact portion 18 is formed using a conductive material, then a phase changeable pattern is formed on the contact portion 18 and the upper electrode is formed on the phase changeable pattern.
FIGS. 4 and 5 are cross-sectional views that illustrate aspects of the conventional phase changeable memory device 30. FIG. 4 illustrates an example in which the contact portion 18a is formed using a phase changeable material. When current is applied to the lower electrode (not shown), heat is generated due to resistance on the boundary surface between the plug 14 and the contact portion 18a. As a result, the state of the phase changeable material is changed. Because the plug 14 has relatively high heat conductivity, however, and the spacer 16 in contact with the contact portion 18a has a relatively low temperature, the edge of the contact portion 18a and the portion in contact with the plug 14 can experience a decrease in temperature. Consequently, when the phase changeable material layer becomes amorphous, the edge of the contact portion 18a may not become completely amorphous, which may result in current leakage.
FIG. 5 illustrates an example in which the contact portion 18a is formed using a conductive material. The phase changeable pattern 20 is formed on the contact portion 18b. As described with reference to FIG. 4, when current is applied to the lower electrode (not shown), the state of the area in contact with the contact portion 18b of the phase changeable pattern 20 changes. In this case, the heat of the area in contact with the contact portion 18b and the area in contact with the edge of the contact portion 18b is transmitted to surrounding portions, so that the state of the areas may be incompletely changed. Because a relatively large amount of current may be required to change the state of a phase changeable material layer completely, power consumption may increase and the data sensitivity may deteriorate.